I filled in some holes today. any ideas on the rest?
ss1 ss1+ SLC IPC SS2
cpu 901 901 801 901 cy601
cpu MHz 20 25 20 25 40
FPU type 3170 3170 3172 3172a ti8847
FPU MHz 20 25 20 25 40
HW context 8 8 8 8 16
PMEG 128 128 128 128 256
cache 64 wt 64 wt 64 wt 64 wt 64 wt
IO cache - - - - -
Max easy ram 64 64 16 48 64
bit simms 9 9 36 9 9
2xx 3xx 4xx 5/x 5e/x
cpu 900 cy601 cy601 cy601 cy601
cpu MHz 16.6 25 33 33 40
FPU type 116[45] ti8847 ti8847 3171 ti8847
FPU MHz ? 25 33 ? ?
HW context 16 16 64 ? ?
PMEG 512 256 1024 ? ?
cache 128 wb 128 wt 128 wb 128 GaAs128 GaAs
IO cache - - 4 - -
Max easy ram 8 32 32 16 16
bit simms ECC 9 ECC kECC kECC
lt opus s4000
cpu cy601 901 mn10501 (64 bit)
cpu MHz 20 25-40 33
FPU type 3171 3172 built in
FPU MHz ? ? -
HW context 8 8 ?
PMEG ? ? ?
cache ? ? on chip: in 6k data 2k
IO cache - - -
Max easy ram 40 64 40
bit simms 9 9 9
> From: Pilotti@Jupiter.SAIC.COM
> FYI, the IPC, having only 128 pmegs (like the SS1 and 1+), can only
> utilize 32MB maximum no matter how many chips you can stuff into the box.
> From gordoni@cs.adelaide.edu.au Wed Feb 6 02:05:18 1991
> pmegs: SLC=128, 4/3xx=256, 4/2xx=512, 4/4xx=1024
> The 4/2xx runs at 16.7MHz, and use a Fujitsu CPU, I don't think it has
> a cache. The SS1, SS1+ run at 20, 25MHz, allow 64M
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